1. Field of the Invention
The invention generally relates to clock signals used in electronic devices. Specifically, embodiments of the invention are related to clock signals used in memory devices.
2. Description of the Related Art
Modern computers systems typically include a memory device which may be accessed and/or controlled by a control device such as a processor or memory controller. In some cases, the memory device may perform operations at a higher speed than the internal clock speed of the control device. Where the memory device performs operations at a higher speed than the clock speed of the control device, the control device may use the internal clock to generate a faster clock signal such as a double-frequency clock signal with twice the frequency of the internal clock used by the control device. The generated double-frequency clock signal may then be provided to the memory device by the control device and used by the memory device to perform necessary operations.
The operations performed by the memory device using the double frequency clock signal may include memory access operations. For example, if the memory device is a double data rate (DDR) type memory device, the memory device may perform read and write operations on both the rising and falling edges of the double frequency clock signal provided by the control device. Memory accesses may also include activation or refreshes of memory addresses.
The memory device may also use the double frequency clock signal to read command data and address data from the control device and provide timing to control circuitry in the memory device. In some cases, the memory device may not receive command and address data as frequently as memory access operations are performed. For example, while memory access operations may be performed on both the rising and falling edges of the double frequency clock signal, the memory device may only read command and address data from the control device on alternate rising edges of the double frequency clock signal (e.g., at the frequency of the internal clock signal of the control device). Accordingly, while the memory device may use the double frequency clock signal to process command data and address data, the memory device may not receive command data and address data at every edge of the double frequency clock signal.
Typically, circuits operating at higher speeds (e.g., the memory device using the double-frequency clock signal) consume more power. Accordingly, in a memory device as described above, where command data and address data are processed using the double-frequency clock signal, the memory device may consume more power. However, where command data and address data in the memory device are not received as frequently as the performance of read and write operations, using the double frequency clock signal to process command data and address data and provide timing to control circuitry in the memory device may be unnecessary. Thus, using the double frequency clock signal to process command data and address data may unnecessarily consume power in the memory device. In some cases, for example, where the memory device is used in a battery operated device (e.g., as part of an embedded system), such increased power consumption may be undesirable.
Furthermore, in some cases, using the double frequency clock signal to process command data and address data may place unnecessary timing requirements on the transmission of command data and address data between the memory device and control device. For example, using the double frequency clock signal to process command data and address data may place inconvenient design constraints on the circuitry in the control device and the memory device which transmits and receives the command data and the process data (e.g., designing the circuitry for the higher speed transmission may be more costly).
Accordingly, what are needed are improved methods and apparatuses for providing clock signals to a memory device.